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Freescale Semiconductor /MKV44F16 /SIM /SOPT4

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Interpret as SOPT4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FTM0FLT0 0 (0)FTM0FLT1 0 (0)FTM0FLT2 0 (0)FTM0FLT3 0 (0)FTM1FLT0 0 (0)FTM3FLT0 0 (0)FTM0TRG0SRC 0 (0)FTM0TRG1SRC 0 (0)FTM0TRG2SRC 0 (0)FTM1TRG0SRC 0 (0)FTM1TRG2SRC 0 (0)FTM3TRG0SRC 0 (0)FTM3TRG1SRC 0 (0)FTM3TRG2SRC

FTM3TRG2SRC=0, FTM1TRG2SRC=0, FTM0TRG0SRC=0, FTM0FLT3=0, FTM0FLT0=0, FTM1TRG0SRC=0, FTM0TRG2SRC=0, FTM0TRG1SRC=0, FTM3TRG0SRC=0, FTM1FLT0=0, FTM0FLT1=0, FTM0FLT2=0, FTM3TRG1SRC=0, FTM3FLT0=0

Description

System Options Register 4

Fields

FTM0FLT0

FTM0 Fault 0 Select

0 (0): FTM0_FLT0 pin

1 (1): CMP0 out
FTM0FLT1

FTM0 Fault 1 Select

0 (0): FTM0_FLT1 pin

1 (1): CMP1 out
FTM0FLT2

FTM0 Fault 2 Select

0 (0): FTM0_FLT2 pin

1 (1): CMP2 out
FTM0FLT3

Selects the source of FTM0 fault 3

0 (0): FTM0_FLT3 pin

1 (1): XBARA output 49
FTM1FLT0

FTM1 Fault 0 Select

0 (0): FTM1_FLT0 pin

1 (1): CMP0 out
FTM3FLT0

FTM3 Fault 0 Select

0 (0): FTM3_FLT0 pin

1 (1): CMP0 out
FTM0TRG0SRC

FlexTimer 0 Hardware Trigger 0 Source Select

0 (0): CMP0 output drives FTM0 hardware trigger 0

1 (1): FTM1 channel match drives FTM0 hardware trigger 0
FTM0TRG1SRC

FlexTimer 0 Hardware Trigger 1 Source Select

0 (0): PDB0 output trigger drives FTM0 hardware trigger 1

1 (1): FTM1 channel match drives FTM0 hardware trigger 1
FTM0TRG2SRC

FlexTimer 0 Hardware Trigger 2 Source Select

0 (0): FTM0_FLT0 pin drives FTM0 hardware trigger 2

1 (1): XBARA output 34 drives FTM0 hardware trigger 2
FTM1TRG0SRC

FlexTimer 1 Hardware Trigger 0 Source Select

0 (0): CMP0 output drives FTM1 hardware trigger 0

1 (1): FTM0 channel match drives FTM1 hardware trigger 0
FTM1TRG2SRC

FlexTimer 1 Hardware Trigger 2 Source Select

0 (0): FTM1_FLT0 pin drives FTM1 hardware trigger 2

1 (1): XBARA output 35 drives FTM1 hardware trigger 2
FTM3TRG0SRC

FlexTimer 3 Hardware Trigger 0 Source Select

0 (0): CMP0 output drives FTM3 hardware trigger 0

1 (1): FTM1 channel match drives FTM3 hardware trigger 0
FTM3TRG1SRC

FlexTimer 3 Hardware Trigger 1 Source Select

0 (0): PDB1 output trigger drives FTM3 hardware trigger 1

1 (1): FTM1 channel match drives FTM3 hardware trigger 1
FTM3TRG2SRC

FlexTimer 3 Hardware Trigger 2 Source Select

0 (0): FTM3_FLT0 pin drives FTM3 hardware trigger 2

1 (1): XBARA output 37 drives FTM3 hardware trigger 2

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data